1. Field
The following description relates to a multi-mode processing technology. For example, the following description relates to a technology for verifying mapped code in a mixed-mode program by a multi-mode reconfigurable processor, and a debugging technology to help find is source code errors.
2. Description of the Related Art
A reconfigurable architecture is an architecture that can alter the hardware configuration of a computing device based on the tasks to be performed by the computing device, thereby enabling optimization at the hardware level for each of the tasks. Such a capability is valuable because one piece of hardware is capable of performing multiple tasks well simply by changing settings of one piece of hardware, instead of requiring multiple pieces of hardware, each optimized for one task, or using a single piece of hardware that is not adaptable, and hence performs at least some of the tasks suboptimally.
When a task is processed using only hardware, it is difficult to efficiently handle even a slight alteration to the way in which tasks are performed, because most hardware is configured to function in a fixed way. On the other hand, when a task is processed using only software, it is possible to alter the software according to the nature of the task, and perform the task using the altered software. However, the task is processed slower than when the task is processed using fixed hardware, in that adapting software for various tasks may not be ideally adapted for optimal performance on the fixed hardware.
A reconfigurable hardware architecture offers the advantages of both hardware and software. More specifically, a reconfigurable hardware architecture ensures the optimal performance of customized hardware while providing the versatility of customized software. For these reasons, the use of reconfigurable architecture has increased, especially in the field of digital signal processing where the same tasks are often repeatedly performed and optimizing those tasks has a meaningful impact on the overall performance.
There are many kinds of reconfigurable architectures. A case in point is Coarse-Grained Array (CGA), which consists of a plurality of Processing Elements (PEs) connected to each other. By changing the way in which the PEs are connected to each other, the CGA may be optimized for performing a specific operation or task.
Recently, a new reconfigurable architecture has been developed, which utilizes a specific PE of a coarse-grained array as a Very Long Instruction Word (VLIW) machine. In such a reconfigurable architecture, there are two execution modes, a CGA mode and a VLIW mode. In a CGA mode, typically, one or more iterative loop operation are processed, and in VLIW mode, typically, general operations other than loop operations are processed. This approach is taken because the CGA mode may be more efficient for handling loops.
A reconfigurable processor based on the CGA has a very complex structure. Such a processor includes a plurality of Functional Units (FUs), a global register file, and a local register file.
If there is data dependency in the CGA, it is difficult for a compiler to analyze and process data. Data dependencies are important to identify because otherwise errors may occur if illegal or corrupted data is generated that does not satisfy the data dependencies. For example, if the compiler fails to overcome the data dependency, a user or programmer cannot even detect an error in binary data mapped in the CGA. As a result, an unintended result may be achieved during execution of a program. In order for reconfigurable hardware architecture to be a viable way of processing data, it must be able to avoid such runtime errors.